Compiler-Enforced Cache Coherence Using a Functional Language

The cost of hardware cache-coherence, both in terms of execution delay and operational cost, is substantial for scalable systems. Fortunately, compiler generated cache management can reduce program seri-alization due to cache-contention; increase execution performance; and reduce the cost of parallel systems by eliminating the need for more expensive hardware support. In this paper, we use the Sisal functional language system as a vehicle to implement and investigate automatic, compiler based cache management. We describe our implementation of Sisal for the IBM Power/4. The Power/4, brieey available as a product, represents an early attempt to build a shared-memory machine that relies strictly on the language system for cache-coherence. We discuss the issues associated with deterministic execution and program correctness on a system without hardware coherence, and demonstrate how Sisal (as a functional language) is able to address those issues.